In general, a semiconductor test apparatus (LSI tester) which runs a test of a semiconductor device inputs a predetermined test pattern signal to a device under test (DUT) as a test target, compares output data output from the device under test with a predetermined expectation value pattern signal, and judges match or mismatch, thereby detecting and judging the quality of the device under test.
This type of semiconductor test apparatus will now be described with reference to FIG. 7. This drawing is a block diagram showing a schematic structure of a conventional general semiconductor test apparatus (LSI tester).
As shown in the drawing, the conventional LSI tester 110 has a level comparator 111 which compares output data from a device under test (DUT) 101 with a comparison voltage in level, a pattern comparator 112 which compares the output data from the device under test 101 with a predetermined expectation value, a flip-flop 121 which is used to input the output data from the device under test 101 to the pattern comparator 112 with a predetermined timing.
In the conventional semiconductor test apparatus having such a structure, a predetermined test pattern signal is first input to the device under test 101 from a non-illustrated pattern generator, and a resultant signal is output as output data from the device under test 101. The output data output from the device under test 101 is input to the level comparator 111. The output that is input to the level comparator 111 is compared with a comparison voltage in level, and output to the flip-flop 121.
In. the flip-flop 121, a signal from the level comparator 111 is held as input data, a strobe from a non-illustrated timing generator is used as a clock signal, and output data is output with a predetermined timing. The output data output from the flip-flop 121 is input to the pattern comparator 112 and compared with predetermined expectation value data output from the pattern generator in the tester, and a comparison result is output. Based on this comparison result, match or mismatch between the output data and the expectation value is detected, and the quality (Pass/Fail) of the device under test 102 is judged.
As described above, in the conventional semiconductor test apparatus (LSI tester), the output data output from the device under test is acquired with a timing of a strobe output with a timing preset in the tester, and this strobe is used as a timing signal output from the timing generator provided independently from the device under test. However, in the conventional semiconductor test apparatus which acquires output data of the device under test by using the independent timing signal output from the tester in this manner, there arises a problem that, for a device having a function for generating an internal clock faster than a system clock, it is impossible to test such a high-speed device which outputs output data with a timing of this internal clock.
In recent years, the progress in increasing a speed of LSIs is significant, and a new semiconductor device as typified by, e.g., an ODR (Octal Data Rate) type device is introduced in order to increase a speed of data transfer. In this type of device, as shown in FIG. 9, an internal clock having a frequency which is n-fold of that of a system clock of a device 101 is generated by a PLL circuit or the like, and data is output with a timing of the internal clock which is faster than the system clock. For example, in the ODR type device, the internal clock which is fourfold of the system clock is generated, and data is output at a DDR (Double Data Rate) in synchronization with both edges, i.e., a rise edge and a fall edge of this internal clock. As a result, data output at a data rate which is eightfold of that of the system clock is realized. The DDR is a mode which performs data transfer with both timings of the rise edge and the fall edge of each internal clock signal, and enables double data transfer with the same clock cycle as compared with an SDR (Single Data Rate) mode which performs data transfer only at the rise edge (or the fall edge) of the internal clock.
In case of performing a test with respect to such a device, data must be acquired with timings of both of the rise edge and the fall edge of a system clock of the, device and at a data rate of an internal clock output at a frequency which is several-fold of that of the system clock.
As described above, however, in the conventional semiconductor test apparatus, output data from the device under test is acquired by using a timing signal output from a timing generator provided independently from the device under test. Therefore, it is impossible to acquire output data with edge timings of a clock output from the device under test and to acquire it at a data rate of an internal clock with a frequency which is several-fold of that of a system clock.
That is, with the structure of the conventional semiconductor test apparatus, a test cannot be conducted with respect to a device which outputs data with edge timings of a system clock and at a data rate of an internal clock faster than a system clock.
The present invention is proposed in order to solve such a problem in the prior art, and it is an object of the present invention to provide a semiconductor test apparatus which enables a test of a device under test which outputs data with edge timings of a system clock and at a data rate of an internal clock faster than the system clock, e.g., a high-speed device as typified by an ODR (Octal Data Rate) type device by acquiring a system clock output from the device under test, and producing a recovery clock having a frequency of an internal clock faster than the system clock with a rise edge timing or a fall edge timing of the system clock.